`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/07/09 20:48:04
// Design Name: 
// Module Name: rst_gen_module
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module global_rst_gen#(
    parameter       RST_CYCLE     =   1   
)(
    input           i_clk                   ,
    output          o_rst                   
);

    logic                 rst=1                ;
    logic  [7 :0]         cnt=0                ;

    assign              o_rst = rst          ;

    initial begin
        if(RST_CYCLE<1)
        $error("RST_CYCLE must be larger than 0!!");
        $finish;
    end

    always_ff @(posedge i_clk) begin
        if(cnt == RST_CYCLE - 1 || RST_CYCLE == 0)
            cnt <= cnt;
        else 
            cnt <= cnt + 1;
    end

    always_ff @(posedge i_clk) begin
        if(cnt == RST_CYCLE - 1 || RST_CYCLE == 0)
            rst <= 0;
        else 
            rst <= 1;
    end

endmodule
